This paper presents a successive approximation ADC (SAR) architecture that takes advantage of the signal-dependent photon shot-noise characteristic of an image sensor. The multi-segmented successive approximation ADC (MS-SAR) applies the sub-ranging technique, where each segment’s conversion step size is scaled according to the photon transfer curve (PTC) of a given pixel. The MS‑SAR selects the appropriate segment with a binary search and then resolves the remaining bits with the SAR register. The ADC is designed to be highly scalable and is targeted for a family of image sensors requiring high-resolution A/D converters. A first prototype high-speed column-parallel image sensor using the MS-SAR architecture was fabricated in a 0.18 µm 5 V/1.8 V CMOS process. Measurement results from this demonstrate that the ADC is capable of resolving 16 bits at the lowest segment with a conversion time of 2.475 us.