This paper presents a 12-bit single slope ADC architecture that uses an on-chip ramp generator for low noise column-parallel CMOS image sensor. An on-chip continuous-time ramp generator is used instead of a discrete-time implementation. This is to reduce the glitch noise caused by a high speed clocking of a discrete-time ramp. Differential topology is adopted to improve the power supply rejection (PSR) performance of the ramp generator. High speed ADC conversion is obtained with accelerated ramp signals by exploiting photon shot noise characteristics of image signals. The ADC is designed to be highly scalable and the architecture is used for a family of image sensors fabricated in TSMC 0.18 µm 3.3 V/1.8 V CMOS process. Measurements show a row noise of 13 uV at gain 24x and 50 uV at gain 3x. The total readout noise is 108 uV at gain 24x and 171 uV at gain 3x.
01 June, 2013