This paper reports progress in our column parallel analog signal chain design strategy, utilizing varying degrees of parallelism for CMOS image sensors. In [1] we investigated the trade-offs for different choices of parallelism and presented an analytical model for optimization of an endoscopic sensor.We continue to use the analytical model and have developed an improved analog readout circuitry that has enabled us to reduced silicon area, achieve higher frame rates, while improving SNR performance. The design is highly scalable and has been implemented in both a high-resolution large format sensor at 60 FPS and a lower-resolution small form factor sensor at 600 FPS. It features a fully differential readout with a high-speed redundant successive approximation A/D converter (SAR-ADC). The analog readout circuitry presented here was tested in a prototype sensor fabricated in 0.18 µm 3.3 V/1.8 V CMOS process. The measured results from the prototype sensor shows the signal chain achieving 248 uV input referred noise with a throughput of 17.5 Mpixel/sec while consuming an estimated 126 uW per pixel column.