This paper describes a high-speed 1.3 Mpix global shutter CMOS image sensor with a column parallel SAR ADC readout. In order to achieve the row time requirements at the maximum frame rate, the SAR ADC utilizes a novel dual reset branch architecture. This approach allows for overlap in the reset sampling phase, without requiring the duplication of the binary weighted capacitors and switches. The time previously used for reset sampling can be reclaimed for the ADC conversion, and the comparator power can be lowered in exchange for a relatively small area penalty. Even though the 5T global shutter pixel does not support direct CDS, the low noise analog signal chain allows us to successfully operate using external CDS for a -6 dB noise improvement.
01 June, 2013