- 2.8 µm pixel array
- 30 frames per second
- On-chip bias and reference generation
- 10-bit pipeline ADC readout
- 2.3 mm x 2.1 mm
- 2.8 V analog supply
- 1.8 V digital supply
- Programmable gain stage
- 30 mW core dissipation
- 0.18 µm CIS process
26 January, 2021
26 January, 2021