- Fully differential pipeline architecture
- 85 mW @ 1.5 V
- > 68 dB SNR
- 1.5 V analog core power
- 2.7 V bandgap power supply
- 1.5 V digital power supply
- 1.2 V differential input
- <1.0 mm2, including bias/clock
- 0.13 µm CIS process
26 January, 2021
26 January, 2021